Posted inElectronics & Semiconductors

NexGen launches SERENO high-performance platform designed for versatile wafer handling and enhanced control

The new concept of ‘smart suit’ called SERENO is ready to order and can be brought to life beginning from Q1 2025.

NexGen Wafer Systems has launched SERENO, a multi-chamber platform designed for Wet Etch and Clean applications. It is a feature-rich platform that can provide both high throughput and exceptional substrate and layer thickness and roughness control through in-situ metrology. Its onboard chemical supply system sustains multiple process chemicals with integrated mixing, blending, and full characterisation, that offer maximum versatility across a variety of operations.

Measuring at less than 12 m² and handling up to 200 wafers per hour, SERENO’s design will provide customers incredible performance and adaptability in wet chemical processing. Developed for FEOL and BEOL uses, SERENO meets the semiconductor industry’s rising needs for greater performance, accuracy, and cost-effectiveness.

The extensibility of the SERENO platform is at its highest in use for the handling of wafers and the management of the whole process and numerous types of substrates are allowed for 6”, 8” and 12” sized wafers. The handling system is designed to accommodate ranged thickness of wafers from ultra-thin wafers less than 100µm to bonded wafers with total thickness of more than 2mm. High performance process chambers along with competitive dispensing and scanning control systems with great chemicals offering great on-wafer performance.

Key features of the SERENO platform include advanced process control, integrated metrology, high-performance chambers, versatile chemical supply, and flexible wafer handling. The use of SERENO is in surface clean; particle removal, polymer residual, back side/ bevel cleaning; incoming wafers, film and metal etch, substrate etch, thinning, stress relief, surface conditioning and visas reveal. The new concept of ‘smart suit’ called SERENO is ready to order and can be brought to life beginning from Q1 2025.

Left to Right: Navin Bishnoi, AVP Central Engineering and India Country manager, Marvell Technology, Srikanth Settikare, VP & MD, India, Microchip Technology, Hitesh Garg, VP & India MD, NXP Semiconductors, Rahul Bedi, VP, Software Products, Automotive Embedded Systems, NXP Semiconductors, Sandeep Bharathi, Chief Development Officer, Marvell Technology, Dr. Chris Miller, Author of Chip War book, Patrick Johnson, Senior Corporate VP & Executive Leadership Team, Microchip Technology, Prof. Vishwani Agrawal, Auburn University, Dr. Satya Gupta, President, VLSI Society of India, and Rajeev Srivastava, Director, Platform Architect Design Enablement – CTO & Bangalore Site Head, NXP Semiconductors
Left to Right: Navin Bishnoi, AVP Central Engineering and India Country manager, Marvell Technology, Srikanth Settikare, VP & MD, India, Microchip Technology, Hitesh Garg, VP & India MD, NXP Semiconductors, Rahul Bedi, VP, Software Products, Automotive Embedded Systems, NXP Semiconductors, Sandeep Bharathi, Chief Development Officer, Marvell Technology, Dr. Chris Miller, Author of Chip War book, Patrick Johnson, Senior Corporate VP & Executive Leadership Team, Microchip Technology, Prof. Vishwani Agrawal, Auburn University, Dr. Satya Gupta, President, VLSI Society of India, and Rajeev Srivastava, Director, Platform Architect Design Enablement – CTO & Bangalore Site Head, NXP Semiconductors
Posted inTechnologyElectronics & Semiconductors

VLSID 2025 kicks off with semiconductor industry leaders and govt dignitaries